The following patent applications are assigned to the assignee hereof and contain subject matter related to the subject matter of the present patent applications:
1. U.S. patent application Ser. No. 08/787,419, entitled xe2x80x9c4F-Square Memory Cell Having Vertical Floating-Gate Transistors with Self-Aligned Shallow Trench Isolationxe2x80x9d, filed on even date herewith for Jeffrey J. WELSER, Hussein I. HANAFI, Stuart M. BURNS, and Waldemar W. KOCON;
2. U.S. patent application Ser. No. 08/792,955, entitled xe2x80x9cSelf-Aligned Diffused Source Vertical Transistors with stack Capacitors in a 4F-Square Memory Cell Arrayxe2x80x9d, filed on even date herewith for Jeffrey J. WELSER, Hussein I. HANAFI, Stuart M. BURNS, Waldemar W. KOCON, and Howard L. KALTER; and
3. U.S. patent application Ser. No. 08/792,952, entitled xe2x80x9cSelf-Aligned Diffused Source Vertical Transistors with Deep Trench Capacitors in a 4F-Square Memory Cell Arrayxe2x80x9d, filed on even date herewith for Jeffrey J. WELSER, Hussein I. HANAFI, Stuart M. BURNS, and Howard L. KALTER.
4. U.S. patent application Ser. No. 08/787,418, entitled xe2x80x9c2F-Square Memory Cell for Gigabit Memory Applications,xe2x80x9d filed on an even date herewith for Jeffrey J. WELSER, Hussein I. HANAFI, and Stuart M. BURNS.
The contents of the above-listed patent applications are incorporated herein by reference.
1. Field of the Invention
The invention is directed to densely packed vertical transistors in a 4F-square memory cell, and methods for making thereof, and more particularly, to memory cells having self aligned source with stack capacitors formed over vertical transistors.
2. Discussion of the Prior Art
There is much interest to scale down densely packed semiconductor devices on an integrated circuit (IC) chip to reduce size and power consumption of the chip, and allow faster operation. In order to achieve the high packing density necessary for Gbit memory application, it is crucial to shrink the size of an individual memory cell as much as possible. FIG. 1 shows a top view of a conventional array 10 of conventional erasable programmable read only memory (EPROM) devices 15, using vertical transistors, such as metal oxide silicon field effect transistors (MOSFETs) with a floating gate layer. The conventional array 10 is described in the following two references. H. Pein and J. D. Plummer, xe2x80x9cA 3-D sidewall flash EPROM call and memory arrayxe2x80x9d, Electron Device Letters, Vol. 14 (8) 1993 pp. 415-417. H. Pein and J. D. Plummer, xe2x80x9cPerformance of the 3-D Pencil Flash EPROM Cell and Memory Arrayxe2x80x9d, IEEE Translations on Election Devices, Vol. 42, No. 11, 1995, pp. 1982-1991.
The conventional array 10 has rows of wordlines 20 and columns of bitlines 25. The size of a cell 27 of the array 10 is 2F by 2Fxcex94, leading to a cell area of 4F2+2Fxcex94. F is the minimum line width of the feature size that can be patterned with lithography. 2F is the cell size along the wordline 20, and 2F+xcex94 is the cell size along the bitline 25. Typically, xcex94 is approximately 0.2F, resulting in a cell area of approximately 4F2+0.4F area achievable using conventional lithography. The additional length A is necessary to separate adjacent wordlines 20.
FIG. 2 shows a partial perspective view of the array 10 of FIG. 1, and FIG. 3 shows a cross sectional view of the vertical MOSFET 15 along a bitline 25.
As shown in FIG. 3, the MOSFET 15 has an n source 30 formed on a P-doped silicon substrate 35. The source 30 is formed after etching the substrate 35 to form a vertical pillar 40, referred to as the body of the MOSFET 15. The pillar 40 acts as the transistor channel and has dimensions of F by F, as shown in FIGS. 1 and 3.
As a result of forming the source 30 after forming the pillars 40, the source 30 is formed around edges of the pillar 40 and is absent from a region 45 located below the pillar 40. Thus, the source 30 does not entirely occupy the footprint of the pillar 40. As shown in FIG. 2, all the MOSFETs 15 of the array 10 have a common source 30, including MOSFETs of different bitlines 25 and different wordlines 20. As shown in FIGS. 2-3, the top of each pillar 40 is doped with N-type material to form n drains 50 of the vertical transistors 15.
A tunnel oxide 60 is formed around the pillar 40 and an oxide spacer 65 is formed on the source 30. Next, a polysilicon floating gate 70, gate oxide 75 and polysilicon gate 20 are formed around the tunnel oxide 60. Note, control gates 20 of individual transistors along the wordline 20 are inter-connected to form the wordline 20.
Because the polysilicon control gate 20 grows uniformly around each vertical MOSFET 15, the spacing between MOSFETs 15 of adjacent rows is slightly larger than the feature size F, e.g., F+xcex94, where xcex94 is approximately 0.2F. This separates adjacent wordlines 20 by amount xcex94, when polysilicon is grown up to a distance of 0.5F. This 0.5F thick polysilicon layer covers the top and sidewalls of the pillars 40, as well as the oxide spacer 65 located on the substrate 35 at the base of the pillars 40.
The 0.5F thick grown polysilicon regions at pillar sidewalls separated by distance F, along each wordline 20, merge with each other. This forms the wordlines 20 around a row of pillars that are separated by F. However, the 0.5F thick formed polysilicon regions at pillar sidewalls separated by distance F+xcex94, the oxide spacer 65 is covered with the 0.5F thick polysilicon.
To separate adjacent wordlines 20, a reactive ion etch (RIE) is performed that removes polysilicon for a thickness of 0.5F. The RIE exposes the top of the pillars 40, as well as the oxide spacer 65 at the base of the pillars that are separated by F+xcex94. The exposed distance of the oxide spacer 65 is xcex94. Thus, the xcex94 separation between adjacent wordlines 20 ensures that control gates 20 of adjacent wordlines are not shorted along the direction of the bitlines 25.
As shown in FIGS. 1 and 2, a first level metal forms bitlines 25 which are orthogonal to the wordlines 20. The first level metal connects drains 50 of MOSFETs 15 along a common bitline 25.
The area of the cell 27 of FIG. 2, is small because the substrate 35 is used as a common source 30 for all the MOSFETs 15 of the array 10. FIG. 4 shows a three dimensional view of another conventional array 90, which is similar to the conventional array 10 of FIG. 2, except for having round pillars 95 instead of square pillars 40 (FIG. 2). As in the array 10 of FIG. 2, the array 90 of FIG. 4 has a common source 30.
The memory function of each cell 27 is achieved by charging or discharging the floating gate region 70. This causes a measurable shift in the threshold voltage of the vertical MOSFET.
In the conventional EPROM cell 27, the tunnel oxide between the floating gate 70 and the transistor channel or pillar 40 is fairly thick, having a thickness of at least 150xc3x85. Therefore charging of the floating gate 70 must be achieved by flowing a large drain current. This generates hot electrons which can tunnel through the tunnel oxide 60, often referred to as hot-electron injection or channel hot electron tunneling. However, channel hot electron tunneling is not suitable for DRAM or xe2x80x9cFlashxe2x80x9d memory application, because channel hot electron tunneling requires high power. This is particularly a problem in the high density arrays necessary for Gbit memories. In addition, tunnel oxide degradation caused by hot electron tunneling is not tolerable for application that require frequent read/write operations.
If the tunnel oxide 60 is made thinner, e.g., xe2x89xa63 nm, direct tunneling between the channel 40 and floating gate 70 is possible. In contrast to hot electron tunneling, direct tunneling is faster resulting in faster write and erase times, requires much lower power, and minimizes tunnel oxide degradation.
However, because the sources 27 of all the MOSFETs are common, setting the bitline and wordline voltages appropriately to write a single cell 27 can still induce hot electron currents in neighboring cells along a wordline 20. This destroys any information in these cells and damages their tunnel oxides 60.
Hence, to make the conventional MOSFETs 15 useful for DRAM/Flash EEPROM applications, the cell must be modified to isolate the source regions 30 between adjacent bitlines 25. This allows use of direct tunneling read/write operations, Furthermore, to achieve the packing density necessary for Gbit memories, the overall cell area must not be increased by these modifications. The cell area must remain approximately 4F-square.
One method for achieving source isolation between bitlines 25 is to pattern isolation lines lithographically between the bitlines 25. Isolation is then be achieved by either a local oxidation of silicon (LOCOS), recessed-LOCOS, or conventional shallow trench techniques.
However, such an isolation method requires lithography. Therefore inter-device 20 lines must be increased from F to at least 2F to avoid shorting adjacent control gates, or wordlines 20 along the bitlines. This increases the inter-device spacing along the bitlines 25 from 1.2F to 2F. Thus, the overall cell size increases from 4F 2+0.4F to at least 6F2. Moreover, lithographic misalignments degrades device behavior. Hence, packing density and/or performance is sacrificed in This scheme.
To increase packing density, instead of forming the vertical MOSFET 15 having the pillar 40, an inverted transistor is formed in a trench etched into the substrate. Such transistor structures are shown in U.S. Pat. Nos. 5,386,132; 5,071,782; 5,146,426 and 4,774,556. The transistors formed in such trenches may be combined with additional planar devices, as discussed in U.S. Pat. No. 4,964,080; 5,078,498. Other memory cells have transistors with a floating body, as discussed in U.S. Pat. No. 5,017,977, does not have separated buried bitlines between transistors. Such conventional cells fail to achieve maximum packing density due to non-self-aligned isolation techniques, or require complex processing methods for fabrication, e.g., selective epitaxial growth, which methods are not suitable for large-scale production.
Instead of using the vertical devices of the memory cell 27 as an EPROM, the vertical transistor 15 without a floating gate, in conjunction with a capacitor, can also be used for DRAM application. FIG. 5 shows a schematic of a typical DRAM cell 100 having a field effect transistor (FET) 105 and a storage capacitor Cs. The other terminal of the storage capacitor Cs is referred to as a plate 115.
When the FET 105 is turned on by an appropriate signal on the wordline W/L, data is transferred between the bitline B/L and storage node 110. The standard one transistor, one capacitor cell 100, shown in FIG. 5, has a theoretical minimum area of 8F2 for a folded bitline, or 4F2 for an open bitline architecture, shown in FIGS. 6 and 7, respectively.
FIG. 6 shows a top view of a conventional folded bitline DRAM cell 120 having active and passing bitlines B/L, B/Lxe2x80x2, respectively, and active and passing wordlines W/L, W/Lxe2x80x2, respectively. The word and bitlines each have a width F. The bit and wordlines are separated from adjacent bit and wordlines by a width F. Thus, the area of the folded bitline DRAM cell 120 is 8F2.
FIG. 7 shows a top view of a conventional open bitline DRAM cell 150, having a bitline B/L and a wordline W/L each having a length F and being separated from adjacent lines of adjacent cells (not shown) by a length F. Thus, The area of the open bitline DRAM cell 150 is 4F2.
Due to the need for contact and isolation spacing, in conventional designs that use planar transistors, it is only possible to obtain these minimum cell sized by creating sub-lithographic features at some level. In addition, if a minimum cell size is to be obtained, it is necessary to reduce the length of the transistor 105 of FIG. 5 as much as possible (down to F). This reduces the gate length. However, shorter gate lengths result in higher leakage currents which cannot be tolerated.
Therefore, the voltage on the bitline must be scaled down accordingly. This reduces the charges stored on the storage capacitor Cs, Thus requiring a larger capacitance to ensure that the stored charge is sensed correctly, for example, to indicate logic 1 or 0.
Increasing the capacitance of the storage capacitor Cs. is achieved by either increasing the capacitor area, or decreasing the effective dielectric thickness located between the capacitor plates. Increasing the capacitor area is becoming more difficult to do without also increasing the cell size, and hence defeating the purpose of shortening the gate in the first place.
Further reducing the dielectric thickness is also difficult, since the thickness of many conventional dielectrics has already reached a minimum practical thickness. To further reduce the dielectric thickness, alternative dielectrics with higher dielectric constant have been explored. While such alternate dielectrics contribute to solving the problem of low charge storage resulting from the decreased bitline voltage, further bitline voltage reduction is limited by the maximum achievable dielectric constant. Accordingly, to further reduce the bitline voltage, an alternative to reducing the gate length of the transistor 105 is necessary.
In light of the foregoing, there is a need for high density memory cells having isolated sources between adjacent bitlines, yet continuous source regions for each individual bitline, to allow cell programming by channel hot electron tunneling.
There is also a need for a memory cell having a proper gate length and capacitor without increasing the lateral area of the cell.
The object of the invention is to provide a memory cell array, and a method of making thereof, that eliminate the problems of conventional memory cell arrays.
A further object of the invention is to provide a folded memory cell array, and a method of making thereof, that has two wordlines passing through each cell, and where one wordline is active and the other is passing for each cell.
These and other objects of the inventions are achieved by a semiconductor device and a method of making thereof. The semiconductor device may be a vertical semiconductor device, such as a MOSFET, which may have a floating gate. An array of these transistors is formed by an array of pillars arranged in rows and columns. The array includes rows of wordlines and columns of bitlines.
The array of these pillars is formed with self-aligned isolation. The vertical device comprises a heavily-doped region on the top of the pillar, followed by a body region with the opposite doping type, then followed by the heavily-doped source region formed, for example, by implantation or by outdiffusion from either heavily-doped oxide, polysilicon, or other suitable material deposited between columns (i.e., bitlines) in the memory array.
The source outdiffusion material may or may not be removed subsequently to annealing. In the case of polysilicon, or other highly conductive source materials, this material may act as a buried xe2x80x9cstrap,xe2x80x9d reducing the resistance of the diffused source region.
The pillars are formed using a two-step etch process that etches column (bitline) and row (wordline) trenches in orthogonal directions. The source regions between columns (bitlines) are separated by etching column trenches, that are parallel to the bitlines and are deeper than the orthogonal row(wordline) trenches. The two step etch thus maintains the continuity of the buried diffused source regions, as well as any additional strapping material still in place, along the array columns for use as buried bitlines for cell access.
The main body of each pillar is encircled by the gate stack that comprises a dielectric layer, (e.g., thermal grown silicon dioxide, referred to as a tunnel oxide), followed by a floating gate material capable of storing charge, (e.g., amorphous silicon, silicon-rich oxide, nano-crystals of silicon, geranium, or other material, nitride, a metal, etc.), followed by a second dielectric layer, (e.g., deposited silicon dioxide), referred to as a gate oxide. Next, a control gate made of polysilicon, for example, is formed around the gate oxide.
Such a memory device or cell may be used as an EEPROM of Flash Memory cell, usually used for non-volatile storage. The vertical memory cell according to the invention has higher speed and endurance than conventional floating gate transistors. In addition, the vertical memory cell may also be used as a DRAM type cell. That is, for DRAM applications, the vertical memory cell replaces a conventional transistor and capacitor combination cell. Thus, the vertical memory cell may be used for either EEPROM or DRAM application.
The tunnel oxide and floating gate may be dispensed with to result in a gate stack that includes the gate oxide and the control gate. This results in a vertical transistor that may be used in conjunction with a capacitor to form a memory cell. The capacitor may be a stack or trench capacitor. Such a memory cell is used for DRAM applications, for example, where charges are stored on the capacitor. In this case, the vertical transistor acts as a switch or transfer device to access the charge for-writing and reading operations.
The gate stack extends between the two heavily-doped regions at the top and base of each pillar. A conductive gate material, (i.e., in-situ, heavily doped polysilicon, with or without silicidation), is deposited on the array to connect pillars along each row, (i.e., wordline), of the array, orthogonal to the bitline direction. This polysilicon is the control gate.
The control gate or wordline around the pillars in the wordline direction (wordline pillars) is separated to form two wordlines or control gates. This is achieved by etching trenches in one direction (bitline trenches), and filling them with desired (e.g., insulating) material. Next, wordline trenches are etched that are orthogonal to the bitline trenches, and polysilicon is deposited on the wafer. An etching step disconnects the polysilicon at the top of the pillars and at the bottom of the wordline trenches.
A folded bitline architecture is preferable in a DRAM cell. This architecture cancels mismatch errors across DRAM arrays. To achieve a folded bitline architecture and to allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations, each pillar must be isolated from one of the wordline control gates running on opposite sides of that pillar. One of the wordline control gates then becomes active and the other passing for each cell.
The invention achieves the folded bitline architecture by raising the threshold voltage of the pillar device on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolation is achieved in a pattern where if one pillar is isolated on the sidewall adjacent to one wordline, each neighboring pillar along columns and along rows is isolated on the sidewall adjacent to the other wordline.
The raising of the threshold voltage of the pillar device on the sidewall of alternate pillars is achieved by, however is not limited to the following methods:
formation of a thicker gate oxide, nitride, oxynitride and other insulating material barrier on the sidewall of the pillar;
angled ion implantation of a dopant into the sidewall of the pillar; and
a vapor phase doping technique by doping or out-diffusion from a solid source like ASG or PSG, BSG the exposed sidewall of the pillar through heating and immersion of the substrate in a dopant source.